Diagnóstico de Circuitos Integrados Analógicos y de Comunicaciones
Resumen
En este artículo se realiza una breve revisión acerca de las estrategias de diagnóstico utilizadas en el diseño y fabricación de circuitos integrados analógicos en general, pero haciendo énfasis en los utilizados en comunicaciones. Se exponen los nuevos paradigmas que rigen el diseño electrónico moderno. A la luz de estos paradigmas, luego se revisan los aspectos más relevantes del diseño microelectrónico moderno, desde una perspectiva cualitativa, así como una exploración breve acerca de los tipos de diagnóstico que podemos encontrar partiendo de las fallas que los originan. Se introducen luego algunas estrategias más usuales para el diagnostico de circuitos integrados de comunicaciones, así como algunas aproximaciones neuronales. Se discute acerca de los aspectos que hacen tan particular el diseño y diagnostico de circuitos integrados de comunicaciones y la comparativa entre las distintas técnicas. Finalmente se propone una estrategia neuronal que combina la técnica MADBIST con una red neuronal para realizar el diagnostico.
Descargas
Citas
RUIZ MERIÑO, Ramón. Notas de clase del curso técnicas de análisis y diseño electrónico UPCT. 179 p. Material no publicado.
ZORIAN, Yervant. System-chips test strategies. En: DESIGN AUTOMATION CONFERENCE. (35th: 1998: San Francisco). San Francisco. ACM: 1998. 6 p.
HAFED, Mohamed; ABASKHAROUN, Nasmy y ROBERTS, Gordon. A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits. En: IEEE journal of solid-state circuits. Vol. 37, No 4 (Abril, 2002); p. 499-514.
KUNDERT, Ken et al. Design of mixed-signal systems-on-a-chip. En: IEEE transactions on computer-aided design of integrated circuits and systems. Vol. 19, No 12 (Diciembre, 2000); p. 1561-1571.
HAFED, Mohamed y ROBERTS, Gordon. A stand-alone integrated excitation/extraction systems for analog BIST application. En: IEEE COSTUM INTEGRATED CIRCUIT CONFERENCE (2000). IEEE: 2000. 4 p.
HAFED, Mohamed y ROBERTS, Gordon. Techniques for high-frequency integrated test and measurement. En: IEEE transactions on instrumentation and measurement. Vol. 52, No 16 (Diciembre, 2003); p. 1780-1786.
HAURIE, Xavier y ROBERTS, Gordon. Arbitrary-precision signal generation for mixedsignal built-in-self-test. En: IEEE transactions on circuits and systems—II : Analog and digital signal processing. Vol. 45, No 11 (Noviembre, 1998); p. 1425-1432.
ABDENNADHER, Salem y SHAIKH, Saghir. Practices in Mixed-Signal and RF IC Testing En: IEEE Design and Test of Computers. (JulioAgosto, 2007); p. 332 – 339.
VEILLETTE, Benoit y ROBERTS, Gordon. A Built-In Self-Test Strategy for Wireless Communication Systems. En: International Test Conference. (1995); p. 930 - 939.
ARABI, Karim y KAMINSKA, Bozena. Design for Testability of Embedded Integrated Operational Amplifiers. En: IEEE Journal of Solid-State Circuits. Vol. 33, No 4 (Abril 1998); p. 573 – 581.
VALDES-GARCIA, Alberto et al. On-Chip Testing Techniques for RF Wireless Transceivers. En: IEEE Design and Test of Computers. (JulioAgosto, 2006); p. 268 – 277.
MILOR, Linda. A Tutorial Introduction to Research on Analog and Mixed-Signal Circuit Testing. En: IEEE transactions on circuits and systems—II : Analog and digital signal processing. Vol. 45, No 10 (Octubre, 1998); p. 1398-1407.
CLAASEN, Theo. System on a Chip: Changing IC Design Today and in the Future. En: IEEE Micro, May-June 2003; p. 20 – 26.
ROBERTS, Gordon. Metrics, Techniques and New Developments in Mixed-Signal Testing. En: Tutorial in Design, Automation and Test in Europe Conference and Exhibition. 2001.
KABISATPATHY, Prithviraj et all. Fault Detection and Diagnosis in Analog Integrated Circuits Using Artificial Neural Network in a Pseudorandom Testing Scheme. En: International Conference on Electrical and Computer Engineering. December 2004. p. 52 – 55.
CZAJA, Zbigniew y KOWALEWSKI, Michal. A New Method for Diagnosis of Analog Parts in Electronic Embedded Systems with Two-Center Radial Basis Function Neural Networks. En: IMEKO TC4 Symposium. September 2008.
STOPJAKOVA, Viera et al. Neural NetworkBased Defect Detection in Analog and Mixed IC Using Digital Signal Preprocessing. En: Journal of ELECTRICAL ENGINEERING. Vol. 57, No. 5. (2006). p. 249 – 257.
] STOPJAKOVA, Viera et al. Neural Network-Based Parametric Testing of Analog IC. En: Proceedings of the 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2002.
HAURIE, Xavier y ROBERTS, Gordon. Arbitrary-precision signal generation for mixedsignal built-in-self-test. En: IEEE transactions on circuits and systems—II : Analog and digital signal processing. Vol. 45, No 11 (Noviembre, 1998); p. 1425-1432.
L. K. Horning, et al, “Measurements of Quiescent Power Supply Current for CMOS ICs in Production Testing”, Proc. Int. Test Conf., 1987, pp. 300-309.
J.M. Soden, and F. Hawkins, “IDDQ Testing and Defect Classes”, Proc. IEEE Custom Int. Circuits Conf., 1995, pp.633-642.
J. Segura, M. Roca, D. Mateo, and A. Rubio, “Built-in dynamic current sensor circuit for digital VLSI CMOS testing”, electronics Letters, vol. 30, pp.1668-1669, 1994.
S-T. Su, R.Z. Makki, and T. Nagle, “Transient Power Supply Current Monitoring - A New Test Method for CMOS VLSI Circuits”, JETTA, vol. 6, pp. 23-43, 1995.
V. Stopjakova, H. Manhaeve, and M. Sidiropulos, “On-chip Transient Current Monitor for Testing of Low-Voltage CMOS IC”, Proc. Design. Autom. and Test in Europe, 1999, pp. 538-542.
A. Germida, Z. Yan, J. F. Plusquellic, and F. Muradali, “Defect Detection using Power Supply Transient Signal Analysis”, Proc. Int. Test. Conf., 1999, pp. 67-76.
M.F. Toner and G.W. Roberts, “A BIST Scheme for an SNR, Gain Tracking, and Frequency Response Test of a Sigma-Delta ADC,” IEEE Trans. On Circuits and Systems-II, Vol. 41, No. 12, pp.1-15, January 1995.
A.K. Lu, G.W. Roberts and D.A. Johns, “A High- Quality Analog Oscillator Using Oversampling D/A Conversion Techniques,” IEEE Trans. on Circuits and Systems-II, vol. 41, no. 7, July 1994, pp. 437444.
B.R. Veillette and G.W. Roberts, “High Frequency Sinusoidal Generation Using Delta-Sigma Modulation Techniques,” IEEE International Symposium on Circuit And Systems, pp.637-640, Seattle, May 1995.
M.J. Ohletz, “Hybrid built-in self-test (HBIST) for mixed analogue/digital integrated circuits,” Proc. European Test Conference, pp. 307-316,1991.
M.F. Toner and G.W. Roberts, “A BIST Technique for a Frequency Response and Intermodulation Distortion Test of a Sigma-Delta ADC,” IEEE VLSZ Test Symposium, pp. 60-65, Cherry Hill, April 1994.
S. Ozev, A. Orailoglu, and C.V. Olgaard, “Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers,” IEEE Design & Test, vol. 19, no. 5, Sept.-Oct. 2002, pp. 82-91.
J. Ferrario, R. Wolf, and S. Moss, “Architecting Millisecond Test Solutions for Wireless Phone RFICs,” Proc. Int’l Test Conf. (ITC 03), IEEE Press, 2003, pp. 1325-1332.
S.S. Akbay et al., “Low-Cost Test of Embedded RF/Analog/Mixed-Signal Circuits in SOPs,” IEEE Trans. Advanced Packaging, vol. 27, no. 2, May 2004, pp. 352- 363.
S. Bhattacharya et. al., “Alternate Testing of RF Transceivers Using Optimized Test Stimulus for Accurate Prediction of System Specifications,” J. Electronic Testing: Theory and Applications, vol. 21, no. 3, June 2005, pp. 323-339.
M. Jarwala, L. Duy, and M.S. Heutmaker, “End-to-End Test Strategy for Wireless Systems,” Proc. Int’l Test Conf. (ITC 95), IEEE Press, 1995, pp. 940-946.
S. Ozev and C. Olgaard, “Wafer-Level RF Test and Dft for VCO Modulating Transceiver Architectures,” Proc. 22nd VLSI Test Symp. (VTS 04), IEEE Press, 2004, pp. 217-222.
J.-S. Yoon and W.R. Eisenstadt, “Embedded Loopback Test for RF ICs,” IEEE Trans. Instrumentation and Measurement, vol. 54, no. 5, Oct. 2005, pp. 1715-1720.
S. Bhattacharya and A. Chatterjee, “Use of Embedded Sensors for Built-In-Test of RF Circuits,” Proc. Int’l Test Conf. (ITC 04), IEEE Press, 2004, pp. 801-809.
J.-Y. Ryu and B.C. Kim, “Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit,” J. Electronic Testing: Theory and Applications, vol. 21, no. 6, Dec. 2005, pp. 571-581.
A. Valdes-Garcia et al., “A CMOS RF RMS Detector for Built-in Testing of Wireless Receivers,” Proc. 23rd VLSI Test Symp. (VTS 05), IEEE Press, 2005, pp. 249-254.
Mahoney, M.: DSP-Based Testing of Analog and Mixed-Signal Circuits, Washington DC, IEEE Computer Soc. Pr. 1987.
IEEE P1149.4 proposal “standard for mixed signal test bus’‘ March 1995, IEEE Standards Department, 445 Hoes Lane, PO Box 1331, Piscataway, NJ 08855-1331, USA.
A. H. Bratt, A. M. D. Richardson, R. J. A. Harvey, and A. P. Dorey: “A design-for-test structure for optimising analogue and mixed signal IC test”, in Proc. European Design & Test Conference, Paris, France, March 1995, pp. 24-32.
L. Wurtz, “Built-in self-test structure for mixed-mode circuit“, IEEE Trans. Instr. and Measur., vol. 42, pp. 25-29, Feb. 1993.
T. Olbrich, A. Richardson, A. Bratt, “Built-In Self-Test (BIST) for high-performance switchedcurrent designs”, in Proc. Intern. Workshop on Mixed Signal Testing, Grenoble, France, June 1995, pp. 246-251.
D Vazquez, A Rueda & J.L. Huertas, “A Dff methodology for active anaolgue filters”, IEEE Mixed Signal Test Workshop, Grenoble, 20th22nd June 1995.
J . Fattaruso, S. Kiriaki, M. Wit, and G. Warwar, “Selfcalibration techniques for a secondorder multibit sigmadelta modulator”,. IEEE Journal of Solid-State Circuits, vol. 28. no. 12, pp. 1216-1223, 1993.
D. Lupea, U. Pursche, H.-J. Jentschel, “BIST: loopback spectral signature analysis”, IEEE Proceedings of the DATE Conference and Exhibition (2003) pp. 478–483.
J.Y. Ryu, B.C. Kim, I. Sylla, A new BIST scheme for 5 GHz low noise amplifiers, Proceedings of IEEE Ninth ETS (2004) pp. 228–233.
M. Soma, Challenges and approaches in mixed signal rf testing, IEEE Proc. 1997; 33–37.
Descargas
Publicado
-
Resumen332
-
PDF208
Cómo citar
Número
Sección
Licencia
Esta obra está bajo una licencia internacional Creative Commons Atribución-NoComercial-CompartirIgual 4.0.
Portal de Ciencia Abierta